RL
Open for requestRTL logic optimisation visualiser
A digital-design laboratory for visualising how synthesis transforms RTL code and comparing area, timing, logic depth, and equivalence before and after optimisation.
- Nuxt
- Vue
- FastAPI
- PostgreSQL
- Python
- Yosys
- Graphviz
- Docker
- Project ID
- GP-EC-1NSM04T
- Domain
- Electronics
- Complexity
- Advanced
- Catalogued
- 21 Aug 2026
- Licence
- Single buyer
- Repository
- Private handover
- Buyer record
- Never public
Included in the project
- RTL editor and synthesis experiment interface
- Netlist, timing, and resource comparison visualisations
- Formal-equivalence and test-bench result modules
- Prepared Verilog designs, experiments, and results
- Complete source code in a private GitHub repository
- Complete project documentation with synopsis, abstract, methodology, logic diagrams, synthesis results, screenshots, and conclusion
- Setup and usage guide