Communication protocol timing simulator
A discrete-event simulator for studying UART, SPI, and I2C timing, configuration errors, bus contention, and waveform-level protocol behaviour.
Project definition
Problem statement
Serial protocols depend on clock rates, sampling positions, edge order, pull-up behaviour, addressing, and device configuration. Many failures appear only as a waveform or intermittent decoded error.
The engineering problem is to model protocol events accurately enough to explain timing behaviour and reproduce common configuration and electrical-level faults without requiring physical hardware.
Project objectives
- Simulate selected UART, SPI, and I2C operating modes with configurable timing.
- Generate digital waveforms and decode frames from simulated signal transitions.
- Detect documented setup, hold, sampling, framing, acknowledgement, and contention errors.
- Inject clock mismatch, delay, noise pulse, missing acknowledgement, and bus-contention scenarios.
- Compare simulator output with manually calculated and prepared reference traces.
System design
System modules
Topology builder
Defines controllers, peripherals, signal lines, protocol mode, clock, and electrical assumptions.
Event simulator
Processes device and signal events in timestamp order with deterministic resolution.
Protocol models
Implements documented UART, SPI, and I2C transmit, receive, addressing, and acknowledgement behaviour.
Waveform and decoder
Displays signal transitions and reconstructs frames, fields, and timing markers.
Fault laboratory
Applies prepared timing and signal faults and records their decoded and waveform effects.
Methodology
System workflow
- 01Configure circuit
The user selects a protocol, device roles, timing values, and a prepared data transfer.
- 02Run baseline
The simulator produces a waveform, decoded frames, and timing measurements.
- 03Inject fault
A clock, delay, line, mode, or acknowledgement fault is applied.
- 04Detect violation
The checker identifies affected edges, fields, and protocol rules.
- 05Compare
Baseline and faulty traces are aligned and their decoded results are explained.
Demonstration scenario
A valid SPI transfer runs in one clock mode and produces the expected decoded bytes. The peripheral is then configured for a different sampling edge. The simulator aligns both waveforms, marks the sampling mismatch, and shows how the received value changes.
Engineering
Technical architecture
- Web application
- Nuxt and Vue for device setup, timeline control, waveform inspection, decoded frames, and comparisons.
- Simulation core
- A deterministic discrete-event engine with protocol device state machines and configurable timestamp resolution.
- Analysis API
- FastAPI for saved scenarios, simulation jobs, waveform data, checks, and experiment results.
- Data layer
- PostgreSQL for configurations, scenarios, expected traces, simulation runs, and measured violations.
- Verification
- Golden traces, property checks, manually calculated examples, and regression tests for protocol modes.
Testing
Evaluation
Evaluation measures
- Timestamp agreement with prepared reference traces
- Correct frame decoding across supported modes and rates
- Detection rate for prepared timing and configuration faults
- False violation rate on valid protocol traces
- Deterministic reproduction of the same scenario
- Simulation and waveform-rendering time across event counts
System boundaries
- The simulator models digital timing and selected electrical assumptions, not complete analogue signal integrity.
- Only documented UART, SPI, and I2C modes are supported initially.
- Results complement and do not replace measurement with an oscilloscope or logic analyser.
- Timing limits are tied to the configured device model and scenario.
Included
- 01Protocol configuration and circuit-topology interface
- 02Discrete-event simulation and waveform viewer
- 03Decoder, timing-check, and fault-injection modules
- 04Prepared protocol scenarios, tests, and results
- 05Complete source code in a private GitHub repository
- 06Complete project documentation with synopsis, abstract, methodology, timing diagrams, simulation results, screenshots, and conclusion
- 07Setup and usage guide
Project record
No buyer information is collected on this page.
- Permanent project ID
- GP-EC-08BN3KY
- Catalogued
- 21 Aug 2026
- Completed
- Pending
- Verified
- Pending
- Demonstration
- Added when ready
Handover
After purchase
- 01Payment is confirmed
The project is marked unavailable and cannot be purchased again.
- 02Repository access is granted
The buyer's submitted GitHub account receives access to the private repository.
- 03The purchase record is delivered
The certification sheet is prepared from the reviewed buyer details and sent privately by email.