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GP-EC-0MD1K4FElectronicsOpen for request

Low-power digital filter design workbench

A digital filter workbench for comparing FIR and IIR designs, fixed-point effects, implementation cost, and measured signal quality under low-power constraints.

  • Nuxt
  • Vue
  • FastAPI
  • Python
  • SciPy
  • C
  • Yosys
  • Docker

Project definition

Problem statement

A filter that meets a frequency-response specification in floating point may lose accuracy or stability after coefficient and arithmetic quantisation.

The engineering problem is to compare filter structures and word lengths against response quality, overflow behaviour, compute cost, memory, and a documented power proxy.

Project objectives

  • Design selected FIR and IIR filters from passband, stopband, ripple, and sampling specifications.
  • Analyse magnitude, phase, delay, poles, zeros, and impulse response.
  • Simulate coefficient and arithmetic quantisation with configurable fixed-point formats.
  • Estimate or measure operations, memory, logic resources, and execution time.
  • Select a design through explicit signal-quality and implementation constraints.

System design

System modules

01

Specification builder

Defines sampling rate, bands, ripple, attenuation, structure, and implementation constraints.

02

Filter designer

Generates selected FIR and IIR candidates and validates stability and numerical conditions.

03

Response analyser

Displays magnitude, phase, group delay, impulse response, poles, zeros, and specification margins.

04

Fixed-point simulator

Models coefficient formats, rounding, saturation, overflow, quantisation noise, and limit behaviour.

05

Implementation profiler

Compares operation count, memory, C execution time, and optional synthesised resource estimates.

Methodology

System workflow

  1. 01
    Enter specification

    The student defines the target response, sample rate, and implementation limits.

  2. 02
    Generate candidates

    Selected FIR and IIR methods produce valid floating-point designs.

  3. 03
    Quantise

    Coefficient and arithmetic word lengths are applied and rechecked.

  4. 04
    Process signals

    Prepared clean and noisy signals run through floating and fixed-point implementations.

  5. 05
    Select tradeoff

    The workbench compares response errors, signal quality, cost, and constraint violations.

Demonstration scenario

A low-pass specification generates FIR and IIR candidates. The student reduces coefficient word length until one design violates stopband attenuation and another develops excessive quantisation error. The workbench compares their signal outputs, operation counts, memory, and measured execution time.

Engineering

Technical architecture

Web application
Nuxt and Vue for specification entry, response plots, signal comparison, and candidate ranking.
Design API
FastAPI for filter creation, analysis, signal jobs, fixed-point runs, and exports.
Signal engine
Python and SciPy for reference designs, frequency analysis, test signals, and numerical checks.
Embedded path
Generated or prepared C implementations for timing and memory profiling under fixed formats.
Hardware estimate
Optional Yosys flow for comparing selected FIR implementations under a fixed target library.

Testing

Evaluation

Evaluation measures

  • Passband ripple, stopband attenuation, cut-off error, and stability
  • Signal-to-noise and reconstruction measures on prepared signals
  • Floating-point and fixed-point output difference
  • Overflow and limit-cycle behaviour across word lengths
  • Operation count, memory, execution time, and optional logic-resource estimate
  • Correct selection of designs that meet all configured constraints

System boundaries

  • Power is represented by documented implementation measures or a calibrated proxy unless physical measurement hardware is used.
  • Hardware estimates depend on the selected synthesis target and constraints.
  • The workbench covers documented digital filter families and fixed-point formats.
  • Final hardware designs require target-specific timing and power verification.

Included

  1. 01Filter specification and design interface
  2. 02Frequency, phase, quantisation, and signal-response visualisations
  3. 03Fixed-point simulation and implementation-cost comparison
  4. 04Prepared signals, filter experiments, and results
  5. 05Complete source code in a private GitHub repository
  6. 06Complete project documentation with synopsis, abstract, methodology, filter diagrams, experiment results, screenshots, and conclusion
  7. 07Setup and usage guide

Project record

No buyer information is collected on this page.

Permanent project ID
GP-EC-0MD1K4F
Catalogued
21 Aug 2026
Completed
Pending
Verified
Pending
Demonstration
Added when ready

Handover

After purchase

  1. 01
    Payment is confirmed

    The project is marked unavailable and cannot be purchased again.

  2. 02
    Repository access is granted

    The buyer's submitted GitHub account receives access to the private repository.

  3. 03
    The purchase record is delivered

    The certification sheet is prepared from the reviewed buyer details and sent privately by email.