RTL logic optimisation visualiser
A digital-design laboratory for visualising how synthesis transforms RTL code and comparing area, timing, logic depth, and equivalence before and after optimisation.
Project definition
Problem statement
Students can observe whether RTL simulation produces the expected output, but it is harder to understand how coding style and synthesis passes change the resulting logic network.
The engineering problem is to run controlled synthesis experiments, visualise structural changes, compare meaningful implementation estimates, and verify that an optimisation preserves intended behaviour.
Project objectives
- Accept a safe synthesizable subset of Verilog designs and prepared test benches.
- Run selected synthesis and optimisation passes under recorded constraints.
- Visualise modules, cells, signals, critical paths, and structural differences.
- Compare cell count, logic depth, timing estimates, and selected resource measures.
- Check simulation results and formal equivalence where supported.
System design
System modules
RTL workspace
Manages versioned source files, top modules, clock constraints, and prepared design examples.
Synthesis runner
Executes allowlisted Yosys flows inside isolated jobs and stores logs, intermediate netlists, and statistics.
Netlist visualiser
Converts synthesis output into navigable module, cell, signal, and path graphs.
Comparison engine
Compares pass sequences, resource counts, logic depth, timing estimates, and changed structures.
Verification module
Runs prepared simulations and supported equivalence checks against the original design.
Methodology
System workflow
- 01Load design
The user opens a prepared RTL design or enters code within the supported synthesizable subset.
- 02Validate
Syntax, top-module, clock, and unsupported-construct checks run before synthesis.
- 03Run flows
A baseline and selected optimisation sequence produce versioned netlists and statistics.
- 04Compare structures
The visualiser highlights changed cells, paths, depth, and resource estimates.
- 05Verify behaviour
Test benches and equivalence checks confirm whether the optimised result preserves intended logic.
Demonstration scenario
A student synthesises two equivalent priority-encoder implementations. The laboratory displays their initial netlists, applies the same optimisation passes, compares cell counts and logic depth, and runs a test bench and equivalence check before accepting the result.
Engineering
Technical architecture
- Web application
- Nuxt and Vue for RTL input, flow selection, graph exploration, metric comparison, and verification results.
- Experiment API
- FastAPI for project files, isolated jobs, synthesis artefacts, comparisons, and exports.
- Synthesis engine
- Yosys for parsing, synthesis, optimisation, statistics, and supported equivalence operations.
- Graph processing
- Python and Graphviz for netlist normalisation, structural matching, path extraction, and diagrams.
- Isolation
- Docker workers with fixed tools, execution limits, read-only templates, and no arbitrary host commands.
Testing
Evaluation
Evaluation measures
- Correct synthesis of prepared valid RTL designs
- Rejection and explanation of prepared invalid or unsupported designs
- Accuracy of cell, connection, depth, and comparison statistics
- Simulation and equivalence results for behaviour-preserving and faulty transformations
- Reproducibility of artefacts under the same tool and configuration versions
- Runtime across prepared design sizes and optimisation sequences
System boundaries
- Results are estimates from the included synthesis flow and target assumptions, not final silicon measurements.
- The first version supports a documented synthesizable Verilog subset.
- Uploaded designs run only inside constrained local workers.
- A successful equivalence result applies only to the checked assumptions and tool configuration.
Included
- 01RTL editor and synthesis experiment interface
- 02Netlist, timing, and resource comparison visualisations
- 03Formal-equivalence and test-bench result modules
- 04Prepared Verilog designs, experiments, and results
- 05Complete source code in a private GitHub repository
- 06Complete project documentation with synopsis, abstract, methodology, logic diagrams, synthesis results, screenshots, and conclusion
- 07Setup and usage guide
Project record
No buyer information is collected on this page.
- Permanent project ID
- GP-EC-1NSM04T
- Catalogued
- 21 Aug 2026
- Completed
- Pending
- Verified
- Pending
- Demonstration
- Added when ready
Handover
After purchase
- 01Payment is confirmed
The project is marked unavailable and cannot be purchased again.
- 02Repository access is granted
The buyer's submitted GitHub account receives access to the private repository.
- 03The purchase record is delivered
The certification sheet is prepared from the reviewed buyer details and sent privately by email.